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sy87702l 1 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 rev.: c amendment: /0 issue date: october 2005 description features sy87702l 3.3v power supply complies with bellcore, itu/ccitt and ansi specifications for applications such as oc-1, oc-3, oc-12, oc-48*, and atm compatible with fddi, gigabit ethernet, fibre channel, 2x fibre channel, smpte 259 and 292, and proprietary applications low power clock and data recovery from 28mbps up to 2.5gbps nrz data stream selectable reference frequencies via programmable multiplier differential pecl and cml high-speed serial outputs line receiver input: no external buffering needed link fault indication 100k ecl compatible i/o available in 64-pin ep-tqfp package the sy87702l is a complete clock recovery and data retiming integrated circuit for data rates from 28mbps up to 2.5gbps nrz. the device is ideally suited for sonet/sdh/ atm, fibre channel, and gigabit ethernet applications, as well as other high-speed data transmission applications. clock recovery and data retiming is performed by synchronizing the on-chip vco directly to the incoming data stream. the vco center frequency is controlled by the reference clock frequency and the selected divide ratio. on- chip clock generation is performed through the use of a frequency multiplier pll and can be used as a clock multiplier unit (cmu). the integrated cmu can provide this clock signal at the tclk outputs. additionally, the tclk output can be selected to provide a copy of the rclk frequency. for sonet/sdh applications, the sy87702l includes a link fault detection circuit. this circuit, enabled by the output of an optical module driving the cd input low, causes the recovery pll of the sy87702l to lock to the reference clock's multiplied frequency under loss-of-signal conditions. this low jitter clock is provided at the rclk outputs and is at the same frequency as that provided at the tclk output. 3.3v 28mbps-2.5gbps anyrate clock and data recovery applications transponders and section repeaters multiplexer's: access, add drop (adm), and terminal (tm) sonet/sdh/atm: -based transmission systems, modules, and test equipment terabit routers and broadband cross-connects fibre optic test equipment hdtv switching and transmission *meets oc-48 jitter tolerance and transfer anyrate is a registered trademark of micrel, inc.
sy87702l 2 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 package/ordering information 64-pin epad tqfp (h63-1) ordering information (1) package operating package lead part number type range marking finish sy87702lhi h64-1 industrial sy87702lhi sn-pb sy87702lhitr (2) h64-1 industrial sy87702lhi sn-pb SY87702LHG (3) h64-1 industrial SY87702LHG with nipdau pb-free bar line indicator pb-free SY87702LHGtr (2, 3) h64-1 industrial SY87702LHG with nipdau pb-free bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. 1 64-pin epad-tqfp 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 21 22 23 24 25 26 27 28 29 48 47 46 45 44 43 42 41 40 39 38 37 36 61 60 59 58 57 56 55 54 53 52 51 50 49 vcosel1 pllrn+ pllrn pllrw+ nc vcca pllsw pllsw+ nc pllsn nc 14 15 16 35 34 33 62 63 64 30 31 32 rdin+ pllrw gnda pllsn+ nc nc nc vcc refclk refclk+ gnd vcc gnd gnd nc divsel3 nc clksel gnd divsel1 divsel2 nc tclkc tclkc+ tclke tclke+ vcco rclkc rclkc+ rclke rclke+ vcco rdoutc rdoutc+ rdoute rdoute+ enpecl gnd rdin lfin nc nc vcco vcc gnd gnd vcc gnd cd freqsel3 freqsel2 freqsel1 vcosel2
sy87702l 3 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 optical module sy87702l cdr/cmu sy877xxl frame detector serial eeprom sel cd lock rx data stream tx data stream carrier detect ref code group data (4, 5, 8, 10, bits) code group strobe code group rate clock alignment detect reference timing (8) rx data rx clock align sy877xxl mux/demux sy877xxl programmable protocol selector note: add second sy877xxl for 16 or 20 bit parallel input and output. txclk system block diagram
sy87702l 4 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 functional block diagram rclke+ rclke rclkc+ rclkc lfin link fault detector tclke+ tclke tclkc+ tclkc vco n/w1/w2/w3 phase detector phase/ frequency detector nc* pllrw pllrw+ pllrn pllrn+ vco n/w1/w2/w3 phase/ frequency detector charge pump n/w divide by 1, 2, 4, 8, 10, 16, 20, 32 freqsel1 freqsel2 freqsel3 enpecl cd rdin+ rdin charge pump n/w mux divsel3 divsel2 divsel1 vcosel2 vcosel1 pllsn+ pllsn pllsw+ pllsw mux clksel rdoutc+ rdoutc rdoute+ rdoute refclk+ refclk * do not connect.
sy87702l 5 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 functional description clock recovery clock recovery, as shown in the block diagram, generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. output pulses from the detector indicate the required direction of phase correction. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which generates the recovered clock. frequency stability, without incoming data, is guaranteed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the pll will be declared out of lock, and the pll will lock to the multiplied frequency of the reference clock. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. this transfer function yields a 30 s data stream of continuous 1's or 0's for random incoming nrz data. the total loop dynamics of the clock recovery pll provides jitter tolerance which is better than the specified tolerance in gr-253-core. pin names inputs rdin [serial data input] differential pecl this differential input accepts the receive serial data stream. an internal receive pll recovers the embedded clock (rclk) and data (rdout) information. the incoming data rate can be within one of ten frequency ranges, or can be one of five specific frequencies, depending on the state of the freqsel and vcosel pins. the rdin pin has an internal 75k ? resistor tied to v cc . refclk [reference clock] differential pecl this input is used as the reference for the internal frequency synthesizer and the training frequency for the receiver pll to keep it centered in the absence of data coming in on the rdin input. the input frequency to refclk is limited to 325mhz or less, depending on the setting on the divsel signals. the refclk pin has an internal 75k ? resistor tied to v cc . cd [carrier detect] pecl input this input controls the recovery function of the receive pll and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. when this input is high, the input data stream (rdin) is recovered normally by the receive pll. when this input is low, the data on the rdin input will be internally forced to a constant low, the data output rdout will remain low, the link fault indicator output lfin forced low, and the clock recovery pll forced to lock onto the clock frequency generated from refclk. vcosel1, vcosel2 [vco select] ttl inputs these inputs select the vco frequency range via either one of three wide-band plls, or a sonet/sdh specific narrow-band pll. only the selected pll is enabled. all other pll s are disabled. please refer to table 1. vcosel1 vcosel2 choice 0 0 sonet/sdh 0 1 1.8 to 2.5ghz 1 0 1.25 to 1.8ghz 1 1 0.650 to 1.30ghz table. 1
sy87702l 6 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 freqsel1, ..., freqsel3 [frequency select] ttl inputs these inputs select the output clock frequency range, as shown in table 2. vcoclk freqsel1 freqsel2 freqsel3 divider 0001 0012 0104 0116 1008 10112 11016 11124 table 2. divsel1, ..., divsel3 [divider select] ttl inputs these inputs select the ratio between the output clock frequency (rclk/tclk) and the refclk input frequency as shown in table 3. please note that the divide by 32 selection, 011 , is only available for use when freqsel are set to 000. refclk divsel1 divsel2 divsel3 multiplier 0001 0012 0104 01132 1008 10110 11016 11120 table 3. clksel [clock select] ttl input this input is used to select either the recovered clock of the receiver pll (clksel = high) or the clock of the frequency synthesizer (clksel = low) to the tclk outputs. enpecl [enable pecl] ttl input this input, when high (enpecl = 1), enables the differential pecl outputs tclke rdoute , and rclke . it also disables the cml outputs, by setting tclkc+, rdoutc+, and rclkc+ logic high and setting tclkc , rdoutc , and rclkc logic low. when set low (enpecl = 0), this signal enables the differential cml outputs tclkc , rdoutc , and rclkc . it also disables the pecl outputs by setting tclke+, rdoute+, and rclke+ logic high and setting tclke , rdoute , and rclke logic low. outputs lfin [link fault indicate] o.c. ttl output this output indicates the status of the input data stream rdin. lfin will go high if cd is high and rdin is within the frequency range of the receive pll (as per alrsel). lfin is an asynchronous output. rdoute [receive data out] differential pecl these ecl 100k outputs represent the recovered data from the input data stream (rdin). this recovered data is sampled on the falling edge of rclk. rdoutc [receive data out] differential cml this is the cml version of rdoute . rclke [receive clock out] differential pecl these ecl 100k outputs represent the recovered clock used to sample the recovered data (rdout). rclkc [receive clock out] differential cml this is the cml version of rclke . tclke [transmit clock out] differential pecl these ecl 100k outputs represent either the recovered clock (clksel = high) used to sample the recovered data (rdout) or the transmit clock of the frequency synthesizer (clksel = low). tclkc [transmit clock out] differential cml this is the cml version of tclke . inputs/outputs pllsn+, pllsn [clock synthesis loop filter] external loop filter pins for the clock synthesis narrow- band pll. pllsw+, pllsw [clock synthesis loop filter] external loop filter pins for the clock synthesis wide-band plls. pllrn+, pllrn [clock recovery loop filter] external loop filter pins for the clock recovery narrow- band pll. pllrw+, pllrw [clock recovery loop filter] external loop filter pins for the clock recovery wide-band plls. others vcc supply voltage vcco output supply voltage vcca analog supply voltage gnd ground gnda analog ground nc these pins are for factory test, and are to be left unconnected during normal use.
sy87702l 7 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 vcosel1 vcosel2 freqsel1 freqsel2 freqsel3 range (mbps) 00000 2488 (oc48) 00001 1244 00010 622 (oc12) 00100 311 00110 155 (oc3) 01000 1800 2500 01001900 1250 (1) 10000 1250 1800 11000650 1300 (2) 11001325 650 (3) 11010163 325 11011109 216 1110082 162 1110155 108 1111041 81 1111128 54 table 4. (4) description general the sy87702l is a complete clock and data recovery circuit, capable of dealing with nrz data rates from 28mbps through to 2.5gbps. a reference pll is used as a frequency synthesizer, both to multiply a clock to the desired transmit rate, and to train the recovery pll in preparation for actual data recovery. vco selection sy87702l has four complete vco circuits. depending of the application and the frequency range, any one of these four perform data recovery. as indicated by the vco selection table, there are three general purpose vcos, covering one of three frequency ranges. however, to extend the range of the device, the output of the vco may be divided down. in the case of the two highest frequency vco, this divisor is always set to 1. for the lowest frequency vco, the freqsel pins select which divisor, and hence, which range of frequencies the vco will work over. in addition, for sonet/sdh applications, there is a narrow band, extremely low jitter pll. it also uses the freqsel divisor to choose the correct sonet/sdh frequency. the various combinations of freqsel and vcosel are not arbitrary, but are limited to the subset shown in table 4, where the range column indicates frequency in mbps. notes: 1. suggested range for fibre channel applications. 2. refclk multiplier of 2 is not allowed in this range. 3. refclk multiplier of 1 is not allowed in this range. 4. combinations of vcosel and freqsel other then those in this table result in undefined behavior, and should not be used.
sy87702l 8 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 loop filter components (1) cml output diagram 100 ? 100 ? 100 ? 100 ? 100 ? sy87702l v cc v cc figure 3. 50 ? load cml output 100 ? 100 ? 200 ? sy87702l v cc figure 4. 100 ? load cml output r 1 c 1 pllsn+ or pllsw+ pllsn or pllsw r1 = 1.2k ? c1 = 1.0 f (x7r dielectric) figure 1. r1 filter component r 2 c 2 pllrn+ or pllrw+ pllrn or pllrw r2 = 1.8k ? c2 = 1.0 f (x7r dielectric) figure 2. r2 filter component note: 1. suggested values. values may vary for different applications. timing waveforms t cpwh refclk rdout t cpwl t dv t dh t odc t odc rclk
sy87702l 9 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 symbol parameter min. typ. max. unit condition v ih input high voltage v cc 1.165 v cc 0.880 v v il input low voltage v cc 1.810 v cc 1.475 v i il input low current 0.5 av in = v il (min) v oh output high voltage v cc 1.075 v cc 0.830 v 50 ? to v cc 2v v ol output low voltage v cc 1.860 v cc 1.570 v 50 ? to v cc 2v v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = 40 c to +85 c 100k pecl dc electrical characteristics symbol parameter min. typ. max. unit condition v cc power supply voltage 3.15 3.3 3.45 v i cc power supply current 400 ma v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = 40 c to +85 c dc electrical characteristics symbol parameter min. typ. max. unit condition v oh output high voltage v cc 0.025 v v ol output low voltage v cc 0.400 v 100 ? environment v cc 0.200 50 ? environment v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = 40 c to +85 c cml dc electrical characteristics (1) note: 1. actual voltage levels and differential swing will depend on customer termination scheme. typically, a 400mv swing is availabl e in the 100 ? environment and a 200mv swing in the 50 ? environment. refer to the cml output diagram for more details. symbol parameter rating unit v cc power supply voltage 0.5 to +7.0 v v in input voltage 0.5 to v cc v i out ecl output current continuous 50 ma surge 100 i cmlout cml output current 30 ma t store storage temperature range 65 to +150 c t a operating temperature range 40 to +85 c note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating condi tions for extended periods may affect device reliability. absolute maximum ratings (1)
sy87702l 10 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 symbol parameter min. typ. max. unit condition v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current +20 av in = 2.7v, v cc = max. +100 av in = v cc , v cc = max. i il input low current 300 av in = 0.5v, v cc = max. i olk output leakage current 500 av out = v cc v ol output low voltage 0.5 v i ol = 4ma v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = 40 c to +85 c ttl dc electrical characteristics symbol parameter min. typ. max. unit condition rclk, tclk output jitter (1) 0.010 ui rms refclk multiplier = 16 lock range/training range 1000 ppm acquisition lock time 15 s > 25% transition density rdin maximum data rate 2.5 gbps refclk maximum frequency 325 mhz t cpwh refclk pulse width high 1.2 ns t cpwl refclk pulse width low 1.2 ns t irf refclk input rise/fall time 1.0 ns (20% to 80%) t odc output duty cycle (rclk/tclk) 45 55 % of ui t re ecl output rise/fall time 200 300 ps 50 ? to v cc 2v t fe (20% to 80%) t rc cml output rise/fall time 65 120 ps no load t fc (20% to 80%) t dv data valid 100 ps t dh data hold 100 ps v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = 40 c to +85 c ac electrical characteristics note: 1. except at oc-48.
sy87702l 11 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 evaluation board schematic sy87702l 2 3 4 5 6 7 8 9 10 11 12 13 17 48 47 46 45 44 43 42 41 40 39 38 37 36 61 60 59 58 57 56 55 54 53 52 51 50 14 15 16 35 34 33 62 63 64 rdin+ nc vcc refclk refclk+ gnd vcc gnd gnd nc divsel3 nc clksel gnd divsel1 divsel2 nc rdin lfin nc nc vcco vcc gnd gnd vcc gnd cd freqsel3 freqsel2 freqsel1 vcosel2 tclkc tclkc+ tclke tclke+ vcco rclkc rclkc+ rclke rclke+ vcco rdoutc rdoutc+ rdoute rdoute+ enpecl gnd vcosel1 pllrn+ pllrn nc pllrw+ pllrw nc vcca gnda pllsw pllsw+ nc pllsn pllsn+ nc nc 1 49 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 67 8 9 10 11 12 vee vcco: pin 37 vcco: pin 42 rdoute+ rdoute rdoutc+ rdoutc rclke+ rclke rclkc+ rclkc tclke+ tclke tclkc+ tclkc vee: pin 48 vcc vee vee:pin 32 vee:pin 26 vee:pin 25 refclk+: force refclk+: sense vcc l4 c11 c12 vee vcca l3 c10 c9 vee:pin 23 refclk : force refclk : sense sw dip-6 s3 1 3 5 7 9 11 12 10 8 6 4 2 header 6x2 jp1 vcc 1 2 3 4 56 7 8 9 10 vee sw dip-5 s1 r5, 5k ? vcc c41 c5 r7 c6 c42 r8 c7 c43 r9 c8 c44 r10 rdin+: force rdin+: sense rdin : force rdin : sense nc: pin 52 nc: pin 53 vee: pin 56 vee: pin 57 vcc: pin 58 vcc l2 c3 c4 1 3 56 4 2 header 3x2 jp4 led vcc d3 r17, 1.7k ? vcco l1 c2 c1 1 2 3 4 56 7 8 9 10 vcc sw dip-5 s2 vcc r47, 130 ? vee vcc r48, 20 ? vee l7 c18 c17 vee: pin 59 r4, 5k ? r3, 5k ? r2, 5k ? r1, 5k ? r23, 5k ? r22, 5k ? r21, 5k ? r20, 5k ? r19, 5k ? r18, 5k ? r11, 1.2k ? r12, 1.2k ? r13, 1.2k ? r14, 1.2k ? r15, 1.2k ? vcc:pin 24 r46, 100 ? r16, 5k ? jp2 d1 d2 vee jp3
sy87702l 12 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 evaluation board i/o termination schemes tclkc v cc r26, 100 ? c19 1 2 j14 rclkc v cc r25, 100 ? c23 1 2 j10 rdoutc v cc r29, 100 ? c27 1 2 j6 v cc r37, 125 ? c31 1 2 j1 r36, 83 ? rdin+:force v ee tclkc+ v cc r27, 100 ? c20 1 2 j13 rclkc+ v cc r24, 100 ? c24 1 2 j9 rdoutc+ v cc r28, 100 ? c28 1 2 j5 rdin+: sense c32 1 2 j2 tclke r30, 330 ? c21 1 2 j12 v ee rclke r32, 330 ? c25 1 2 j8 v ee rdoute+ r34, 330 ? c29 1 2 j4 v ee v cc r39, 125 ? c33 1 2 j17 r38, 83 ? rdin :force v ee tclke+ r31, 330 ? c22 1 2 j11 v ee rclke+ r33, 330 ? c26 1 2 j7 v ee rdoute+ r35, 330 ? c30 1 2 j3 v ee rdin : sense c34 1 2 j18 tclk rclk rdout rdin outputs outputs inputs inputs notes: 1. for ac coupling, include capacitors c19 thru c31, c33, c35 and c37. 2. if dc coupling, remove resistors r36 thru r43. 3. for 50 ? cml systems, include resistors r24 r29. 4. for 100 ? cml systems, see figure 3.
sy87702l 13 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 refclk nc (future inputs rev. output) v cc r41, 125 ? c35 1 2 j15 r40, 83 ? refclk+:force v ee nc: pin 52 r44, dni c39 1 2 j21 v ee refclk+: sense c36 1 2 j16 nc: pin 53 r45, dni c40 1 2 j22 v ee v cc r43, 125 ? c37 1 2 j19 r42, 83 ? refclk :force v ee refclk : sense c38 1 2 j20 vee: pin 59 c45 0.01 f vcc: pin 58 c46 0.01 f vee: pin 57 c47 0.01 f vee: pin 56 c48 0.01 f vee: pin 48 c49 0.01 f vcco: pin 42 c50 0.01 f vcco: pin 37 c51 0.01 f vee: pin 32 c52 0.01 f vee: pin 26 c53 0.01 f vee: pin 25 c54 0.01 f vcc: pin 24 c55 0.01 f vee: pin 23 c56 0.01 f
sy87702l 14 micrel, inc. m9999-102405 hbwhelp@micrel.com or (408) 955-1690 64 lead epad h quad flatpack (h64-1) rev. 02 package ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 64-pin epad-tqfp package micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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